Rapid advances of very large scale integrated circuit (VLSI) technologies have made design of integrated circuits increasingly complex and time consuming. Computer-Aided Design (CAD) has become a necessity to speed up and improve the quality of VLSI design. Of all the phases in designing application specific VLSI circuits, physical layout takes up a major portion of the turn-around time.
In creating a physical layout of an application specific VLSI circuit, a computer layout is first generated. Generally, the computer layout is created by arranging a number of individual blocks or "logic cells" according to predetermined schematics. The functionality and design of individual logic cells may be predetermined and stored on a computer system as a standardized design. Such design techniques can save considerable time, as it is no longer necessary for an integrated circuit designer to custom design each individual gate and transistor in an integrated circuit. Rather, the circuit designer breaks down a new circuit design into a number of known (or new) cell designs and then combines these cells appropriately to generate a circuit design which performs a desired function. Each of the logic cells contains a number of terminals for implementing into the integrated circuit. These logic cells are commercially available.
To "tape-out" such a computer layout, commercial "place-and-route" CAD tools, such as Cell3.TM. from Cadence Design Systems, Inc., of San Jose, Calif., can be utilized. More particularly, place-and-route CAD programs are used 1) to arrange logic cells and other elements to optimize their interconnections and the overall surface area and 2) to define the routing region and to select channels to connect the logic cells and elements. To perform the tasks mentioned above, a place-and-route CAD tool requires as input a predetermined number (including reserves) of predefined logic cell types (e.g., AND-gate, OR-gate, flip-flop, etc.). Information related to the logic cells along with the required terminal connections are provided to the place-and-route CAD tool in a data file called "netlist". In response, the place-and-route CAD tool outputs a computer layout.
Using the computer layout generated as a blueprint, a number of base, contact, and metal layers defining the elements and interconnections of the VLSI circuit are created in silicon through a combination of semiconductor processes namely depositing, masking, and etching. When combined, these layers form the VLSI circuit. Depending on the complexity of the application specific VLSI circuit, each circuit may involve multiple base layers, multiple contact, and multiple metal layers. This process is widely known as tape-out.
Following tape-out, for various reasons including design changes, modifications are subsequently required to delete as well as add logic elements and interconnections from the VLSI circuit. When this occurs, an engineering change order (ECO) is generated to document the desired changes. Next, the computer layout generated earlier is modified using the commercial place-and-route CAD tool to incorporate the desired changes. Under the prior art, extra logic cells of different types are included in the original computer layout as reserves in case new elements are needed. However, due to limitations inherent in the software environment (e.g., capability to handle a limited number of variables), the place-and-route CAD tool requires that these extra logic cells be of predefined types and numbers. Because the types of the logic cells are predefined as AND gates, OR gates, flip-flops, etc., modifications are limited to changing the logic cells connectivity. Such inflexibility may cause disastrous consequences. For example, in adding logic elements as required under an ECO, a logic cell of a certain type may not be available for implementing a desired function. As a result, either the desired function must be deleted or the process of generating a computer layout with the desired logic cells must be restarted. As such, neither one of these options are desirable.
Even if the right type logic cells are available for adding, the layout engineer must still make the proper connections. Because the locations of the logic cells are fixed, it is sometimes not possible to provide the desired connections given existing obstacles and various space constraints in the layout. In addition, it is a painful and time consuming task to identify the extra logic cells and provide the proper wiring to properly connect the added cells. Because of the increasing complexity of VLSI circuits, the layout engineer must work with as many as four different layout layers at a time. Given the complexity of the task, under the prior art, the turn-around time to incorporate the desired ECO changes is generally high.
Thus, a need exists for a system and method to preserve as much of the information generated from the original layout as possible to allow ECO changes to be made faster and more efficiently.